1. Field of the Invention
The present invention relates to a layout interconnections verifying apparatus and a method for verifying layout interconnections. More particularly, the present invention relates to a layout interconnections verifying apparatus that can be used to judge whether or not layout interconnections satisfy a requirement with respect to a current based on whether or not a current flowing through each branch interconnection of the layout interconnections on a semiconductor device exceeds a predetermined current value, and a method for verifying layout interconnections that can do the same.
2. Description of the Related Art
In a semiconductor device design, a layout of interconnections is designed after circuit elements such as transistors and the like are placed. After the layout of the interconnections, if the current flowing through the interconnection is locally concentrated and exceeds the predetermined current value (standard value), it is expected that the interconnection is broken by causing electromigration. As avoiding such situation, the layout design is verified whether or not the portion, through which the current exceeding the standard value flows, exists in the interconnections after the layout.
Typically, the layout interconnections include a plurality of branch portions. Also, the elements such as the transistors and the like are placed at the end thereof. Usually, the layout interconnections are verified by replacing the interconnections after the layout with a interconnection model. FIG. 1 is a view showing a model of a part of the interconnections included in the semiconductor devices after the layout design. In this example, element terminals T21 to T25, such as sources or drains of the transistors or the like are connected to ends of branch interconnections Br21 to Br25, respectively.
With reference to FIG. 1, the values of the currents flowing through the element terminals T21 to T25 are determined in advance by simulation and the like. The current value of each branch interconnection is obtained by following the branch interconnection route with respect to the current value of each element terminal. For example, when the route, in which the current value I21 is outputted from the element terminal T21 and the current value I22 is outputted from the element terminal T22, are followed, the total of the currents flowing into a node N22 and the total of the currents flowing out from the node N22 are equal. Thus, the current value of the branch interconnection Br27 between the node N22 and the node N23 is obtained as I21+I22. The above-mentioned technique for calculating the current value of each branch interconnection is disclosed in, for example, Japanese Laid Open Patent Application JP H07-153845 A (FIG. 14), and Japanese Laid Open Patent Application JP 2004-70548 A. When the current value of each branch interconnection is obtained, whether or not there is the possibility of the occurrence of the electromigration is verified based on a width of each branch interconnection and an interconnection material and the like.
Incidentally, the branch interconnection for the mutual connection between the interconnections having the same potential is laid in the layout interconnections. In this case, a loop may be generated in the route. FIG. 2 is a view showing the model of the layout interconnections including the loop. In FIG. 2, the loop portion is generated by the branch interconnections for the mutual connections among nodes N31, N32, N33 and N34. When this loop is included in the interconnections, the current values of the branch interconnections in the loop portion cannot be obtained by simply adding the current values of element terminals T31 to T33 along the route.
Here, in the model shown in FIG. 2, when all of the branch interconnections are replaced with resistances to analysis them as a resistance circuit network, it is possible to obtain the current values of all the branch interconnections including the loop portion. However, this case has a problem that the calculation is complex which makes the time required to obtain the current value very long.